Monolithic inverter IC chips, in which integrated parts such as a lateral IGBT, a lateral diode, an analog circuit and a digital circuit are constructed on a SOI (Silicon on insulator) substrate, are developed and utilized. A performance of the inverter IC is mainly determined by the integrated lateral IGBT and the lateral diode. The important performance indexes of the lateral IGBT are a low on-state voltage and a high switching speed, and the important performance indexes of the lateral diode are also a low on-state voltage and a high switching speed. Specifically, it is necessary for the lateral IGBT to maintain the low on-state voltage and the high switching speed without controlling a lifetime, which is performed by irradiating an electron beam. Additionally, reducing a carrier concentration of an on-state by reducing an efficiency of hole injection to a collector is very important.
Conventionally, a double-layered collector region includes a large P-well region having a low impurity concentration and a small P+-type region having a high impurity concentration. The P-well region and the P+-type region are both in ohmic contact with a collector electrode so as to suppress a total amount of acceptor impurities in the collector region. Further, a N-type buffer layer that surrounds the low impurity concentration P-well region and the high impurity concentration P+-type region provides a donor-type impurity effect so that hole injection is restricted. Therefore, the efficiency of hole injection is reduced as shown in JP 3415441 (corresponding to U.S. Pat. No. 6,133,607).
However, based on a study by inventors of the present invention, it is found that the double-layered structure of the collector region causes an increase in variation of on-state voltage in a case where a fall time tf is set to 0.3 μsec or less.
The low on-state voltage and the high switching speed are in a trade-off relationship. Therefore, basically the fall time decreases with the increasing on-state voltage. However, as shown in JP 3415441 (corresponding to U.S. Pat. No. 6,133,607), the trade-off relationship between the low on-state voltage and the high switching speed no longer exits in a structure in which the double-layered collector region is in ohmic contact with the collector electrode. Further, the fall time can not be reduced by a sacrifice of the on-state voltage and the variation of the on-state voltage is increased. In the conventional IGBT, in which the collector electrode is in ohmic contact with the collector region, the fall time does not decrease stably with the increasing on-state voltage after the fall time is reduced to a certain level. Therefore, the switching speed can not be improved higher than a certain level. According to an analysis by inventors of the present invention, a surface of the P-well channel layer having a low impurity concentration is in an unstable contact with the collector electrode in a case where a surface impurity concentration of the P-well channel layer is set to, for example, 1×1017 cm−3 and the collector electrode is made of aluminum including 1% of silicon. The unstable contact between the surface of the P-well channel layer and the collector electrode causes the variation of the on-state voltage.